1. Field of the Invention
The present invention relates to static memory cells and, more specifically, to memory cells, the state of which is not modified by the collision of heavy ions on a sensitive area of the cell.
2. Discussion of the Related Art
Electronic equipment can, in certain conditions, especially in space, be submitted to particle bombardment, in particular by heavy ions. When the drain of a MOS-type transistor biased in a determined way is crossed by a heavy ion, the MOS transistor generates a parasitic pulse on its drain. Such a disturbance phenomenon, currently called upset phenomenon, can have disturbing effects, and especially change the state of the memory cell due to the parasitic effect on various transistors of the cell.
International patent application WO 94/22144 illustrates from page 1-line 15 to page 3-line 26, FIGS. 1A and 11B, a conventional static memory cell. It includes MOS-type transistors forming two inverters mounted head-to-tail. These transistors store a binary logic state and its complementary state. The cell further includes two access lines to write into or read from the cell. The inverters are supplied with a high supply potential Vdd and with a low supply potential Vss. Each inverter is formed by a P-channel transistor and an N-channel transistor, connected in series. The sources of the P-channel and N-channel transistors receive, respectively, potential Vdd and potential Vss. Their drains are interconnected and form the inverter output. Their control gates are interconnected and form the inverter input. A high logic state, noted "1", will correspond to a potential substantially equal to high supply potential Vdd. A low logic state, noted "0", will correspond to a potential substantially equal to low supply potential Vss.
The sensitive transistors are, generally, the N-channel transistors in the off state, the drains of which are at a potential close to high supply potential Vdd, and the P-channel transistors in the off state, the drains of which are at a potential close to low supply potential Vss. In the case of an N-channel transistor, if a heavy ion crosses the depleted area located in the vicinity of the drain, a negative pulse is generated, and the potential thereof is momentarily drawn to potential Vss. Conversely, in the case of a P-channel transistor, a positive parasitic pulse is generated on its drain, and the potential thereof is momentarily drawn to potential Vdd. There then exists a risk of modification of the states of the transistors forming the memory cell, and of a modification of the state of the datum stored in this cell. To minimize this risk of modification, it has been attempted to make so-called hardened memory cells, which are not sensitive to radiation.
A first solution is of technological nature and aims at making transistors which are intrinsically not sensitive to the effects of radiation. A disadvantage of this type of solution is that it is generally difficult to implement. It is also expensive, since it is necessary to develop and use for production specific technologies.
A second solution provided in U.S. Pat. No. 5111429 consists of using redundant memories. This solution has two significant disadvantages. It generates a significant increase in the silicon surface area, for an equal storage capacity. It also generates high power consumption.
A third solution, provided for example in patent application WO 94/22144, consists of modifying the architecture of the memory cells to minimize the risk of modification of the stored states. Typically, the modification of the architecture consists of adding additional transistors (six, for patent application WO 94/22144). This third solution thus generally has a disadvantage in terms of occupied silicon surface and of consumed current.